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B.Eng DegreeFaculty of Faculty of Engineering & TechnologyComputer Engineering
CPE 301: Computer Architecture & Processor Design
Datapath/control design, pipelining, structural/data/control hazards, cache hierarchy, virtual memory, and bus arbitration.
Course Overview
Datapath/control design, pipelining, structural/data/control hazards, cache hierarchy, virtual memory, and bus arbitration. Curriculum Structure & Core Modules: • 1. Processor Performance Metrics: Clock Cycle Time, CPI, Execution Time, and Amdahl's Law • 2. Single-Cycle...
What You'll Learn
- Design single-cycle and multi-cycle datapaths and control units for a subset of the RISC-V/MIPS ISA.
- Analyze instruction pipelining performance, CPI equations, and throughput gains.
- Design hazard resolution hardware: pipeline stalls, data forwarding units, and dynamic branch prediction.
- Evaluate multi-level cache memory organizations (direct-mapped, set-associative) and write policies.
- Model virtual memory, Translation Lookaside Buffers (TLB), page replacement, and memory protection.
Requirements
- Completion of CPE 214.
Degree Programme Curriculum Context
This course is a curriculum unit of the Bachelor of Engineering (B.Eng.) in Computer Engineering degree framework in Nigeria.
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Course Curriculum
Open-access academic curriculum. All foundational lectures available to read free.
8 Chapters
•16 Lecture
•24h
1. Processor Performance Metrics: Clock Cycle Time, CPI, Execution Time, and Amdahl's Law: Theoretical Foundations, Mathematical Modeling & System Architecture
CPE 301 • 300 Level • Computer Engineering Chapter 1: Processor Performance Metrics: Clock Cycle Time, CPI, Execution Time, and Amdahl's Law — Theoretical Foundations, Mathematical Modeling & System Architecture Course: CPE 301: Computer Architecture & Processor Design Curriculum: NUC-CCMAS-CPE Accreditation: COREN-CPE-OBE Standard: IEEE/ACM-CE2024 1. Pedagogical Scope &am...
2. Processor Performance Metrics: Clock Cycle Time, CPI, Execution Time, and Amdahl's Law: Worked Engineering Problems, Design Computations & Simulation Protocols
CPE 301 • 300 Level • Computer Engineering Chapter 1: Processor Performance Metrics: Clock Cycle Time, CPI, Execution Time, and Amdahl's Law — Worked Engineering Problems, Design Computations & Simulation Protocols Course: CPE 301: Computer Architecture & Processor Design Curriculum: NUC-CCMAS-CPE Accreditation: COREN-CPE-OBE Practice: COREN ERM / IEEE Design Standards 1....
1 hour 30 minutes
3. Chapter 1 Formative Assessment: Processor Performance Metrics: Clock Cycle Time, CPI, Execut
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Instructor
PAMCET Learning Team
Institutional Course Curation · PAMCET
Qualifications:
PAMCET Learning Team — Institutional Course Curation, Digitpen Hub LtdMy Skills:
- Curriculum Curation
- Course Content Review
- Learning Outcome Design
- Course Publishing & Quality Assurance
- Platform Content Operations
Reviews
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Free
Course Includes
8 Chapters
16 Lectures
2 - 4 weeks
Skill Level intermediate
Taught in English
Lifetime Access
Certification of Completion
Category: University - Computer Engineering
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