CPE 314: Embedded Systems & FPGA Implementation Laboratory

By PAMCET Learning Team

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CPE 314: Embedded Systems & FPGA Implementation Laboratory

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Last UpdateSep 17, 2026

About Course

Hands-on and simulated bench: FreeRTOS multithreading on ARM, Verilog HDL synthesis on FPGA boards, and hardware-in-the-loop.

Course Includes

8 Chapters
16 Lectures
24h Course Duration
Skill Level intermediate
Taught in English
Lifetime Access

Course Includes

8 Chapters
16 Lectures
24h Course Duration
Skill Level intermediate
Taught in English
Lifetime Access

What You'll Learn

Implement a preemptive multi-tasking FreeRTOS application with inter-task queues and semaphores on physical hardware.
Write, simulate, and synthesize a complete digital logic subsystem in Verilog HDL for an FPGA target device.
Constrain FPGA clock frequencies and I/O pin assignments using Synopsys Design Constraints (SDC / XDC).
Debug live running FPGA designs using embedded logic analyzers (Xilinx Integrated Logic Analyzer - ILA).
Integrate an embedded microprocessor with an FPGA accelerator via a standard memory-mapped bus (e.g. AXI-Lite).

Requirements

Completion of CPE 313. Access to an FPGA development board (e.g. Xilinx Artix-7 / Intel Cyclone IV).

Instructor

PAMCET Learning Team

The PAMCET Learning Team is the institutional curriculum and content group behind course publishing on this platform. PAMCET (Professional and Academic Management Centre for Education and Training) is operated by Digitpen Hub Ltd, a company registered in Lagos, Nigeria. Courses credited to the PAMCET Learning Team are structured, organized, and published centrally by the platform rather than authored by a single named individual instructor — each course's syllabus, learning outcomes, and content are reviewed before publication under this institutional account. For questions about a specific course or to report a content issue, please use the platform's Help & Support or Contact Us pages.

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Course Curriculum

1. FreeRTOS Multitasking Lab: Task Creation, Priority Scheduling, and Queue Data Transfer: Theoretical Foundations, Mathematical Modeling & System Architecture

1 hour 30 minutes

2. FreeRTOS Multitasking Lab: Task Creation, Priority Scheduling, and Queue Data Transfer: Worked Engineering Problems, Design Computations & Simulation Protocols

1 hour 30 minutes

3. Chapter 1 Formative Assessment: FreeRTOS Multitasking Lab: Task Creation, Priority Schedulin

CPE 314: Embedded Systems & FPGA Implementation Laboratory

Rating

Enrolled Students0

Last UpdateSep 17, 2026

About Course

Hands-on and simulated bench: FreeRTOS multithreading on ARM, Verilog HDL synthesis on FPGA boards, and hardware-in-the-loop.

Course Includes

8 Chapters
16 Lectures
24h Course Duration
Skill Level intermediate
Taught in English
Lifetime Access

Course Includes

8 Chapters
16 Lectures
24h Course Duration
Skill Level intermediate
Taught in English
Lifetime Access

What You'll Learn

Implement a preemptive multi-tasking FreeRTOS application with inter-task queues and semaphores on physical hardware.
Write, simulate, and synthesize a complete digital logic subsystem in Verilog HDL for an FPGA target device.
Constrain FPGA clock frequencies and I/O pin assignments using Synopsys Design Constraints (SDC / XDC).
Debug live running FPGA designs using embedded logic analyzers (Xilinx Integrated Logic Analyzer - ILA).
Integrate an embedded microprocessor with an FPGA accelerator via a standard memory-mapped bus (e.g. AXI-Lite).

Requirements

Completion of CPE 313. Access to an FPGA development board (e.g. Xilinx Artix-7 / Intel Cyclone IV).