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B.Eng DegreeFaculty of Faculty of Engineering & TechnologyComputer Engineering
CPE 208: Sequential Logic & Digital Systems Design
Latches, flip-flops, synchronous state machines (Mealy/Moore), counters, shift registers, timing, and Verilog introduction.
Course Overview
Latches, flip-flops, synchronous state machines (Mealy/Moore), counters, shift registers, timing, and Verilog introduction. Curriculum Structure & Core Modules: • 1. Bistable Multivibrators: Latches (SR, D) vs Edge-Triggered Flip-Flops (SR, D, JK, T) • 2. Flip-Flop Timing...
What You'll Learn
- Compare operation, characteristic equations, and excitation tables of SR, D, JK, and T flip-flops.
- Design synchronous sequential circuits using formal state diagrams, state tables, and state minimization techniques.
- Synthesize Mealy and Moore finite state machines (FSM) with robust reset and error-handling states.
- Design multi-bit synchronous up/down counters, ring counters, Johnson counters, and universal shift registers.
- Analyze setup time, hold time, clock skew, and metastability in high-speed clocked sequential systems.
Requirements
- Completion of CPE 207.
Degree Programme Curriculum Context
This course is a curriculum unit of the Bachelor of Engineering (B.Eng.) in Computer Engineering degree framework in Nigeria.
Earn Your Certificate
Showcase your skills with a certificate! Complete the course, submit your project, and earn your certificate. Here's a sample of what you'll receive to show off your accomplishments.
Course Curriculum
Open-access academic curriculum. All foundational lectures available to read free.
8 Chapters
•16 Lecture
•24h
1. Bistable Multivibrators: Latches (SR, D) vs Edge-Triggered Flip-Flops (SR, D, JK, T): Theoretical Foundations, Mathematical Modeling & System Architecture
CPE 208 • 200 Level • Computer Engineering Chapter 1: Bistable Multivibrators: Latches (SR, D) vs Edge-Triggered Flip-Flops (SR, D, JK, T) — Theoretical Foundations, Mathematical Modeling & System Architecture Course: CPE 208: Sequential Logic & Digital Systems Design Curriculum: NUC-CCMAS-CPE Accreditation: COREN-CPE-OBE Standard: IEEE/ACM-CE2024 1. Pedagogical Scope & Beh...
2. Bistable Multivibrators: Latches (SR, D) vs Edge-Triggered Flip-Flops (SR, D, JK, T): Worked Engineering Problems, Design Computations & Simulation Protocols
CPE 208 • 200 Level • Computer Engineering Chapter 1: Bistable Multivibrators: Latches (SR, D) vs Edge-Triggered Flip-Flops (SR, D, JK, T) — Worked Engineering Problems, Design Computations & Simulation Protocols Course: CPE 208: Sequential Logic & Digital Systems Design Curriculum: NUC-CCMAS-CPE Accreditation: COREN-CPE-OBE Practice: COREN ERM / IEEE Design Standards 1. Compre...
1 hour 30 minutes
3. Chapter 1 Formative Assessment: Bistable Multivibrators: Latches (SR, D) vs Edge-Triggered F
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Instructor
PAMCET Learning Team
Institutional Course Curation · PAMCET
Qualifications:
PAMCET Learning Team — Institutional Course Curation, Digitpen Hub LtdMy Skills:
- Curriculum Curation
- Course Content Review
- Learning Outcome Design
- Course Publishing & Quality Assurance
- Platform Content Operations
Reviews
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Free
Course Includes
8 Chapters
16 Lectures
2 - 4 weeks
Skill Level beginner
Taught in English
Lifetime Access
Certification of Completion
Category: University - Computer Engineering
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