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CPE 405: VLSI Design & System-on-Chip (SoC) Architecture
CMOS layout, stick diagrams, Elmore delay, AMBA bus (AXI/AHB/APB), IP cores, Design for Testability (DFT), and ASIC flow.
Course Overview
CMOS layout, stick diagrams, Elmore delay, AMBA bus (AXI/AHB/APB), IP cores, Design for Testability (DFT), and ASIC flow. Curriculum Structure & Core Modules: • 1. CMOS Integrated Circuit Fundamentals: Inverter Transfer Characteristics, Noise Margins, and Parasitics • 2. MOS...
What You'll Learn
- Draw CMOS layout stick diagrams and apply scalable lambda design rules for DRC and LVS clean circuits.
- Calculate propagation delays, parasitic capacitances, and Elmore RC delays in CMOS combinational networks.
- Design interconnect architectures using the ARM AMBA on-chip bus family (AXI, AHB, APB).
- Integrate reusable third-party intellectual property (IP) cores into cohesive System-on-Chip (SoC) platforms.
- Implement Design for Testability (DFT) circuits including scan chains, scan flip-flops, and Built-In Self-Test (BIST).
Requirements
- Completion of CPE 301 and CPE 304.
Degree Programme Curriculum Context
This course is a curriculum unit of the Bachelor of Engineering (B.Eng.) in Computer Engineering degree framework in Nigeria.
Earn Your Certificate
Showcase your skills with a certificate! Complete the course, submit your project, and earn your certificate. Here's a sample of what you'll receive to show off your accomplishments.

Course Curriculum
Open-access academic curriculum. All foundational lectures available to read free.
CPE 405 • 400 Level • Computer Engineering Chapter 1: CMOS Integrated Circuit Fundamentals: Inverter Transfer Characteristics, Noise Margins, and Parasitics — Theoretical Foundations, Mathematical Modeling & System Architecture Course: CPE 405: VLSI Design & System-on-Chip (SoC) Architecture Curriculum: NUC-CCMAS-CPE Accreditation: COREN-CPE-OBE Standard: IEEE/ACM-CE2024 1. Ped...
CPE 405 • 400 Level • Computer Engineering Chapter 1: CMOS Integrated Circuit Fundamentals: Inverter Transfer Characteristics, Noise Margins, and Parasitics — Worked Engineering Problems, Design Computations & Simulation Protocols Course: CPE 405: VLSI Design & System-on-Chip (SoC) Architecture Curriculum: NUC-CCMAS-CPE Accreditation: COREN-CPE-OBE Practice: COREN ERM / IEEE De...
Academic Ecosystem & Connected Pathways
Deepen your studies across connected learning pathways in the PAMCET academic network:
Instructor
PAMCET Learning Team
Institutional Course Curation · PAMCET
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PAMCET Learning Team — Institutional Course Curation, Digitpen Hub LtdMy Skills:
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Course Includes
Download Syllabus & Study Guide
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